Self-awareness has a long history in biology, psychology, medicine, engineering and (more recently) computing. In the past decade this has inspired new self-aware strategies for emerging computing substrates (e.g., complex heterogeneous MPSoCs) that must cope with the (often conflicting) challenges of resiliency, energy, heat, cost, performance, security, etc. in the face of highly dynamic operational behaviors and environmental conditions. I will review our early efforts towards deploying a computational self-awareness framework for achieving cross-layer resilience in heterogeneous MPSoCs through two facets. First, I will summarize our work on CyberPhysical-Systems-on-Chip (CPSoC), a new class of sensor-actuator rich many-core computing platforms that intrinsically couples on-chip and cross-layer sensing and actuation to support computational self-awareness. The CPSoC design paradigm achieves computational self-awareness through introspection (i.e., modeling and observing its own internal and external behaviors) combined with both reflexive and reflective adaptations via cross layer physical and virtual sensing and actuations applied across multiple layers of the hardware/software system stack. Second, I will summarize our work on variability-aware memory management for nanoscale computing systems, building on the efforts of the NSF Variability Expeditions Project. After describing the challenges for dependability across the memory hierarchy, I will show how to opportunistically exploit hardware variations in on-chip and off-chip memory at the system level through the deployment of variation-aware software stacks, and the opportunities that computational self-awareness brings to make these systems more resilient and self-adaptive.