Alberto L. Sangiovanni-Vincentelli is the Edgar L. and Harold H. Buttner Chair at the EECS Department, UC Berkeley. He graduated from the Politecnico di Milano in 1971. He co-founded Cadence and Synopsys, the two leading EDA companies. He is on the Board of Directors of Cadence, KPIT, Expert.ai, Cy4Gate, Exein, and Chairman of the Board of Quantum Motion, Phononic Vibes, Innatera and Phoelex. He is a member of the advisory board of Walden International and Xseed, of the Scientific Advisory Board of the Italian Institute of Technology and the Chair of the Strategic Board and of the International Advisory Board for the Milano Innovation District. He is a member of the Advisory Board of the Politecnico di Milano and honorary Professor at Politecnico di Torino. He was the President of the “Comitato Nazionale dei Garanti della Ricerca” and of the Strategy Committee of Fondo Strategico Italiano. He consulted for companies such as Intel, HP, Bell Labs, IBM, Lendlease, Samsung, UTC, Lutron, Kawasaki Steel, Fujitsu, Telecom Italia, Pirelli, GM, BMW, Mercedes, Magneti Marelli, and ST Microelectronics. He authored 19 books, 2 patents and over 1,000 papers. He is Fellow of the IEEE and ACM, and a member of the National Academy of Engineering. He is the recipient of several academic honors, and research awards including the IEEE/RSE Wolfson James Clerk Maxwell Medal “for groundbreaking contributions that have had an exceptional impact on the development of electronics and electrical engineering or related fields” and the BBVA Frontiers of Knowledge Award in the Information and Communication Technologies category with the following motivation: “for transforming chip design from a handcrafted process to the automated industry that power today’s electronic devices”. Alberto holds four Honorary Doctorates from University of Aalborg, KTH, AGH and University of Rome, Tor Vergata.

In the late 1980s and early 1990s, the most prestigious conferences and journals in electronic design were full of contributions related to the use of AI and in particular, of expert systems for layout, logic and high-level synthesis. The consensus was that the field of EDA was going to be nominated by EDAs. Several companies were founded in this domain. However, these approaches fell off from the interest of the community because of the superiority in quality of results demonstrated by tools that were based on specialized algorithms for layout and synthesis. Are we in the same situation today with Deep Learning and in general, Machine Learning? We will investigate how ML algorithms work and what are the problems to face when applying these techniques to CPS and electronic design.

Alfonso Rodríguez has a MSc on Industrial Electronics (2014) and a PhD on Electrical and Electronics Engineering (2020), both by Universidad Politécnica de Madrid (UPM). Currently, he is an Associate Professor at UPM and carries out its research activity as a member of the Center of Industrial Electronics and Multimodal Systems (CEIMM). His main research interests are high-performance embedded systems, reconfigurable computing, (open, custom) computer architectures (e.g., RISC-V), and digital IC design, both with commercial and open-source EDA tools. His work is backed by 12 publications in JCR-indexed journals, as well as by 26 conference publications, 1 book, and 1 book chapter.  He has actively participated in projects of different nature, both European (MYRTUS, A-IQ Ready, Rigoletto, ODE4EC-PIV) and Spanish (TALENT, TALENT2CONCEPT, OASIS, UPM-Indra Chair on Microelectronics).  He is part of the steering committee of the DASIP workshop, which he also co-chaired in 2023.

The EDA market has long been dominated by a handful of major vendors, who have driven the industry to an unprecedented level of maturity and capability. The flip side of this concentration is a business model sustained by license costs that escalate sharply with design complexity. Only organizations able to generate the revenue needed to absorb those costs can realistically access the technology, which raises a serious barrier to ASIC adoption worldwide, particularly for small companies, spin-offs, and academia.

This is beginning to change. Driven by the open hardware movement, with RISC-V as its main exponent, there is now a worldwide effort to develop, mature, and adopt open source EDA tools. Tools such as Yosys and OpenROAD, or complete frameworks like LibreLane demonstrate the growing readiness of the technology, today increasingly underpinned by the emergence of open PDKs (SKY130, GF180MCU, IHP130) with operational fabrication access.

This seminar presents the principles and the opportunities these tools unlock. A hands-on session lets attendees work directly with an open source flow on a real-world design scenario, from RTL to layout.

Andrés Otero holds a BSc and MSc in Telecom Engineering from Universidade de Vigo (2007), as well as an MSc in Industrial Electronics (2009) and a PhD in Industrial Electronics (2014), both from Universidad Politécnica de Madrid (UPM). Currently, he is an Associate Professor at UPM and carries out his research activity as a member of the Center for Industrial Electronics and Multimodal Systems (CEIMM), where he leads the Applied Electronic Technology research group (GTEA). His main research interests are high-performance embedded systems, reconfigurable computing, embedded and edge artificial intelligence, neuromorphic hardware, and digital IC design with both commercial and open-source EDA tools. His work is backed by 23 publications in JCR-indexed journals, more than 50 conference publications, and 3 book chapters. He has actively participated in projects of various kinds, both European (MYRTUS, RIGOLETTO, A-IQ Ready, CERBERO, KYKLOS4.0) and Spanish (MANIAS, TALENT, TALENT2CONCEPT, UPM-Indra Chair on Microelectronics), serving as Principal Investigator on several of them.

The EDA market has long been dominated by a handful of major vendors, who have driven the industry to an unprecedented level of maturity and capability. The flip side of this concentration is a business model sustained by license costs that escalate sharply with design complexity. Only organizations able to generate the revenue needed to absorb those costs can realistically access the technology, which raises a serious barrier to ASIC adoption worldwide, particularly for small companies, spin-offs, and academia.

This is beginning to change. Driven by the open hardware movement, with RISC-V as its main exponent, there is now a worldwide effort to develop, mature, and adopt open source EDA tools. Tools such as Yosys and OpenROAD, or complete frameworks like LibreLane demonstrate the growing readiness of the technology, today increasingly underpinned by the emergence of open PDKs (SKY130, GF180MCU, IHP130) with operational fabrication access.

This seminar presents the principles and the opportunities these tools unlock. A hands-on session lets attendees work directly with an open source flow on a real-world design scenario, from RTL to layout.

Jeronimo Castrillon is a professor in the Department of Computer Science at the TU Dresden, where he is also affiliated with the Center for Advancing Electronics Dresden (CfAED), the Center for Scalable Data Analytics and Artificial Intelligence Dresden/Leipzig (ScaDS.AI), and the Barkhausen Institut. He is the head of the Chair for Compiler Construction, with research focus on programming and design methodologies as well as computer architectures for complex emerging computing systems. He received a degree in Electronic Engineering from the Pontificia Bolivariana University in Colombia in 2004, his masters degree from the University of Lugano in Switzerland in 2006 and his Ph.D. degree (Dr.-Ing.) with honors from the RWTH Aachen University in Germany in 2013. In 2014, Prof. Castrillon co-founded Silexica GmbH/Inc, a company that provided programming tools for heterogenous architectures, now with Xilinx/AMD. In 2023, he co-founded Xronos, a company that develops tools and services for safe cyber-physical systems. Prof. Castrillon has more than 150 international publications, is Senior Member IEEE, Senior Member ACM, is a member of the editorial board of the ACM TODAES and IEEE TC, and serves as deputy coordinator of the Software Campus in Germany. In 2025 he received a Consolidator Grant from the European Research Council (ERC). 

The demise of scaling laws in micro-electronics has led to the so-called golden era of computer architectures. This includes massive parallelism, hardware specialisation, new technologies and non Von-Neumann computing models. This talk discusses high-level programming and compiler abstractions for specific application domains such as high-performance computing, cyber-physical systems and machine learning. Concretely, we discuss coordination programming languages, methodologies to exploit and adapt to heterogeneous computing systems, and current efforts to model and compile for non Von-Neumann computing accelerators. The latter includes abstractions and optimizations flows for reconfigurable systems as well as near and in-memory computing architectures. We report on experiences building such abstractions and optimisations in an extensible framework built upon the MLIR compiler infrastructure. We believe that this kind of unification and automation is key to more quickly navigate the heterogeneous landscape of emerging accelerators, enable efficient architecture exploration, and to bring the benefits of emerging architectures to a boarder range of applications. 

Battista Biggio (MSc 2006, PhD 2010) is a Professor of Computer Engineering at the University of Cagliari, Italy, and research co-director of AI Security at the sAIfer lab (www.saiferlab.ai). He has been attacking machine-learning (ML) models well before adversarial examples were discovered, in the context of cybersecurity applications such as spam filtering, malware detection, web security, and biometric recognition (PRJ 2018). His team was the first to formalize attacks on ML models as optimization problems and to demonstrate gradient-based evasion (ECML-PKDD 2013) and poisoning (ICML 2012) attacks on ML algorithms, playing a leading role in the establishment and advancement of this research field. His seminal paper on “Poisoning Attacks against Support Vector Machines” won the 2022 ICML Test of Time Award. His work on “Wild Patterns” won the 2021 Best Paper Award and Pattern Recognition Medal from Elsevier Pattern Recognition. Prof. Biggio has managed several industrial, national, and EU-funded projects, and regularly serves as Area Chair for top-tier conferences in machine learning and computer security, such as NeurIPS and the IEEE Symposium on Security and Privacy. He is an Associate Editor-in-Chief of Pattern Recognition and chaired IAPR TC1 (2016-2020). He is a Fellow of IEEE, IAPR, and AAIS, a Senior Member of ACM, and a member of ELLIS.

Machine learning systems are everywhere — filtering spam, detecting malware, and now writing code and making decisions on our behalf. But these systems can be fooled, sometimes surprisingly easily. An image can be slightly modified to make a classifier see a different object than what is depicted. A few crafted inputs slipped into training data can quietly corrupt a model’s behavior. For twenty years, security researchers and attackers have been locked in a back-and-forth: every new defense inspires a cleverer attack, and every clever attack inspires a new defense.
In this talk, I’ll walk through that history — starting with the earliest attacks on spam and malware detectors, through the discovery of “adversarial examples” that fool image classifiers, and up to the brand-new challenges posed by large language models and autonomous AI agents. Along the way, I’ll explain the core ideas of adversarial machine learning in plain terms: what makes a model vulnerable, how attackers find its weak points, and why building a truly robust defense has proved so hard. I’ll also get a bit critical: why do so many proposed defenses look great on paper but fail in practice? Part of the answer lies in how we evaluate these systems — we often lack rigorous, scalable ways to stress-test models under adversarial or unusual conditions, and we don’t have good tools to catch evaluation errors, biased datasets, or models that are right for the wrong reasons. I’ll share some of our lab’s recent work tackling these problems and try to convince you that the path to trustworthy AI isn’t a single, unbreakable model, but rather AI embedded as a carefully engineered component within a larger, more resilient system with a defense-in-depth approach.

Ingrid Verbauwhede is a full professor at the KU Leuven, in the COSIC research group. Her area of expertise is hardware security. It includes system and architecture design, embedded or cloud systems, ASIC and FPGA design and design methodologies.
Ingrid is a fellow of IEEE and of IACR, and a member of the Royal Academy of Belgium for Sciences and Arts. She received two advanced ERC grants in 2016 and 2021 respectively. Her most recent awards are the 2023 the IEEE Donald O. Pederson Solid-State Circuits Award and the 2024 EDAA Achievement Award. In 2025, she received the FWO Excellence Prize. According to Google Scholar, Ingrid has an H-index of 99 with more than 35000 citations. Her list of publications and patents can be found at the following link: https://www.esat.kuleuven.be/cosic/people/ingrid-verbauwhede/ and on Google Scholar: https://scholar.google.com/citations?user=ZyG1ZGgAAAAJ&hl=en&oi=ao
Ingrid is also a co-founder of the start-up company Belfort Labs, which focuses on acceleration for computing on encrypted data, and which is based on the results of her advanced ERC grants.

Post-quantum cryptography (PQC) is a new class of cryptography that resists mathematical attacks from quantum computers. Indeed, PQC relies on new mathematical foundations for which no efficient quantum algorithms have been discovered yet to break them.

PQC is at the basis of new standardization efforts for public key cryptography and digital signatures. Its lattice-based mathematical structures are also the foundation for fully homomorphic encryption schemes, and computing on encrypted data in general.

This presentation will focus on the digital design challenges of these novel cryptographic structures on existing or special purpose semiconductor hardware platforms: CPU, GPU, FPGA, ASIC and on cyber-physical systems. Post-quantum cryptography put unique constraints in terms of area, throughput, latency, power and energy consumption.
While practical attacks from quantum computers are currently not yet possible, CPS are subject to all current electronic manipulation attacks including side-channel, fault- and micro-architectural attacks. We will demonstrate this with up-to-date attacks and present recent research results to address these challenges.

Prof. Theocharis (Theo) Theocharides holds a Ph.D. in Computer Science and Engineering from the Pennsylvania State University. He is an Associate Professor and the Department Chair, at the Department of Electrical and Computer Engineering, at the University of Cyprus and the Director of Research of the KIOS Research and Innovation Centre of Excellence. His research is focused on embedded, mobile and adaptive systems, tinyML, embedded computer vision and pattern recognition architectures and models, and intelligent system-level monitoring and dynamic reconfiguration for performance, energy and reliability of Systems-on-Chip. He has authored/co-authored more than 220 papers and book chapters in internationally acclaimed books and peer-reviewed scientific journals and conferences. He is a senior member of the IEEE and the IEEE Computer Society, a member of the ACM, a member of the HiPEAC Network of Excellence. He is an Area Editor for IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), an  Associate Editor for ACM’s Computing Surveys, Transactions on Embedded Computing Systems, Transactions on Emerging Technologies for Computing Systems (JETC), and for the IEEE Design and Test magazine. He also serves on several Steering/Organizational and Technical Program Committee boards of various IEEE/ACM Conferences, most recently being the Technical Programme Committee Chair of the 2025 edition of the Design, Automation and Test in Europe (DATE). Together with his students, they have worked extensively and pioneered work on hardware acceleration for machine learning and computer vision applications, including object detection, pattern recognition and depth estimation from stereoscopic video, yielding real-time, high frame-rates and low-power, suitable for emerging embedded vision systems, mobile robotics, and cyber-physical systems. His present work focuses on leveraging bioinspired algorithms for the development of hardware-friendly neural inference and tinyML applications and distributed embedded computer vision applications. Further, along with his students, they work on vision-based robotic collaboration for various monitoring and visual information extraction algorithms, involving smart camera networks, robot swarms, and autonomous aerial (drones) and terrestrial robots. He was selected as an IEEE CEDA Distinguished Lecturer for the 2025-2026 period.

Edge AI, a term which describes inference and sometimes learning when deployed on severely resource-constrained devices, is rapidly transforming how and where machine learning and inference is executed. This lecture introduces the foundations of Edge AI, focusing on how advances in low-power sensors, embedded processors, specialized AI accelerators, and mature off-the-shelf platforms have made on-device intelligence both practical and scalable, democratizing AI in a way. We will examine the hardware–software stack that facilitates Edge AI, including sensing modalities, microcontrollers, system-on-chip solutions, model optimization techniques, and deployment toolchains that enable inference under strict constraints of energy, memory, and latency.
Building on these fundamentals, the lecture will identify key challenges such as resource limitations, performance, robustness, energy efficiency, and privacy. We will also discuss their deployment potential in emerging applications such as autonomous systems, wearable computing, and critical infrastructure monitoring. The lecture will review representative approaches spanning model compression, efficient model/hardware architectures, event-driven processing, and collaborative edge–cloud intelligence.
Finally, the lecture will discuss forward-looking directions and design guidelines, including bio-inspired computation, in-sensor and on-device learning and processing, and hardware–algorithm co-design. The overall goal is for the attendees to understand what makes Edge AI feasible today, what limits it, and how the field may evolve as the edge matures into an independent agent with its own “decision” capabilities.

Professor Ayse Coskun is the Chief Scientist at Emerald AI, a startup focused on enabling power flexibility in data centers. She is also a full professor in the Electrical and Computer Engineering Department at Boston University, where she leads the Center for Information and Systems Engineering and serves as Associate Dean for Research at the College of Engineering (currently on leave from BU). Prof. Coskun is widely recognized as a leading academic authority on orchestrating data center power demand in response to power grid needs. Her research group has published groundbreaking work in this area, helping shape the emerging field of flexible, grid-aware computing. Her broader research applies AI and machine learning to optimize cloud and high-performance computing systems. She has received numerous honors for her contributions, including the Ernest Kuh Award for energy-efficient system-level design and an IBM Faculty Award for applying AI-based methods in DevSecOps. Earlier in her career, Prof. Coskun worked in industry at Sun Microsystems (now Oracle). She recently served as Deputy Editor-in-Chief of IEEE Transactions on Computer-Aided Design and holds a PhD in Computer Science and Engineering from the University of California, San Diego.

This talk explores how the rapid growth of AI is transforming data centers into major power consumers—and how, with the right technologies, data centers can become valuable grid resources instead. The talk will discuss emerging approaches to making AI workloads “power-flexible”,
enabling data centers to dynamically adjust their consumption in response to grid conditions while meeting performance constraints. Drawing from real world deployments, the talk highlights how grid-interactive data centers can accelerate interconnection and support a more resilient power grid and a more sustainable AI growth.

Lana Josipović is an Assistant Professor in the Department of Information Technology and Electrical Engineering at ETH Zurich. Prior to joining ETH Zurich in 2022, she received a Ph.D. in Computer Science from EPFL. Her research interests include reconfigurable computing and electronic design automation. She is a recipient of various research awards, including the EDAA Outstanding Dissertation Award, EPFL Doctorate Award, Google Ph.D. Fellowship in Systems and Networking, and Best Paper Awards at ISFPGA’20, FPL’24, and IWLS’26. She is an Area Editor for IEEE TCAD, Associate Editor for ACM TRETS, and ACM TODAES, and served as general, program, and topic chair of several international conferences and workshops, including IWLS, FCCM, FPL, DAC, and DATE.

Custom hardware accelerators, such as FPGAs and ASICs, are a promising solution to deal with our increasing computational demands, as they offer high parallelism and energy efficiency. However, a major barrier to their success and adoption is the difficulty of hardware design–a task available exclusively to a limited number of hardware experts. In this talk, I will discuss the challenges and limitations of current hardware design approaches. I will outline hardware compilation techniques that overcome these limitations and make hardware design broadly accessible, fast, and reliable. Finally, I will share my vision for future advancements in hardware design and its accessibility to users from various application domains.

Paolo Azzoni is the Secretary General of INSIDE Industry Association (formerly Artemis-IA), the industry association that serves as the European Technology Platform for research, design and innovation on Intelligent Digital Systems and their technology ecosystems. INSIDE is one of the three private members of the Chips-JU, the tripartite partnership between the European Commission, the Participant States and private entities, mobilizing more than 11 billion euro to safeguard, consolidate, and strengthen the Electronic Components and Systems value chain in Europe. In this context, he is the lead delegate in the Chips Ju Governing Board and the co-chairman of the ECS Strategic Research and Innovation Agenda, a funding-agnostic document describing the major challenges and priorities in the Electronic Components and Systems domain for the next 10 years. He is also the Head of European Technology Programmes at EUROTECH Group, planning and directing industrial research projects, in the areas of cyber-physical systems, intelligent systems, machine-to-machine technologies, edge computing, internet of things and digitalization solutions. Before joining EUROTECH, he was involved in academic lecturing and research in the areas of hardware formal verification, hardware/software co-design and co-simulation, advanced hardware architectures and operating systems. He holds a Master Degree in Computer Science and a second Master Degree in Intelligent Systems.

INSIDE Industry Association (https://inside-association.eu/) is the European Technology Platform for research, design, and innovation on Intelligent Digital Systems. The presentation explores INSIDE’s role within the Chips Joint Undertaking (Chips JU), a major EU initiative that is responsible for the implementation of the European Chips Act. The talk outlines the structure and strategic goals of Chips JU, particularly its focus on capacity building and R&I and highlights the contribution of the association in shaping European research and innovation. The presentation also covers the ECS Strategic Research and Innovation Agenda (SRIA), a comprehensive roadmap co-created by over 280 European experts to steer Europe’s digital transformation. Through collaboration across industry, academia, and policy, INSIDE fosters a sustainable and inclusive ecosystem for electronic components and systems innovation, ultimately supporting Europe’s technological sovereignty and competitiveness.