Alberto L. Sangiovanni-Vincentelli is the Edgar L. and Harold H. Buttner Chair at the EECS Department, UC Berkeley. He graduated from the Politecnico di Milano in 1971. He co-founded Cadence and Synopsys, the two leading EDA companies. He is on the Board of Directors of Cadence, KPIT, Expert.ai, Cy4Gate, Exein, and Chairman of the Board of Quantum Motion, Phononic Vibes, Innatera and Phoelex. He is a member of the advisory board of Walden International and Xseed, of the Scientific Advisory Board of the Italian Institute of Technology and the Chair of the Strategic Board and of the International Advisory Board for the Milano Innovation District. He is a member of the Advisory Board of the Politecnico di Milano and honorary Professor at Politecnico di Torino. He was the President of the “Comitato Nazionale dei Garanti della Ricerca” and of the Strategy Committee of Fondo Strategico Italiano. He consulted for companies such as Intel, HP, Bell Labs, IBM, Lendlease, Samsung, UTC, Lutron, Kawasaki Steel, Fujitsu, Telecom Italia, Pirelli, GM, BMW, Mercedes, Magneti Marelli, and ST Microelectronics. He authored 19 books, 2 patents and over 1,000 papers. He is Fellow of the IEEE and ACM, and a member of the National Academy of Engineering. He is the recipient of several academic honors, and research awards including the IEEE/RSE Wolfson James Clerk Maxwell Medal “for groundbreaking contributions that have had an exceptional impact on the development of electronics and electrical engineering or related fields” and the BBVA Frontiers of Knowledge Award in the Information and Communication Technologies category with the following motivation: “for transforming chip design from a handcrafted process to the automated industry that power today’s electronic devices”. Alberto holds four Honorary Doctorates from University of Aalborg, KTH, AGH and University of Rome, Tor Vergata.

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Dr. Daniel Newbrook is a member of the Cyber Phyical Systems (CPS) research group in the School of Electronics and Computer Science. Working at SoClabs in affiliation with Arm and the Arm-ECS research centre, our mission is to develop reusable SoC designs for the integration of novel hardware, making research in this area easier for academics and researchers. As well as making educational material for the design and implimentation of SoCs and ASICs. He studied Electronic Engineering at the University of Southampton, recieving a first class bachelors degree in 2017. He then studied for his PhD under the supervision of Kees de Groot in the area of semiconductor material and device development centred around thermolectric energy harvesting.

SoC labs assist researchers to innovate in System on Chip development and realisation building on Arm-based computing architectures. We help to simplify the transition path from FPGA deployment to full ASIC flow, supporting high-quality tier 1 publications by allowing researchers to present actual measured power/energy usage and performance in silicon. This is achieved by providing a global community with resources on technologies, design/implementation flows and by sharing projects. Within these projects are some of SoC labs reference designs including custom IP to full open-source SoC reference designs that can be used and adapted by researchers. This session explores the design methodologies for a SoC with a custom accelerator. Starting from the design and specification of a custom accelerator, all the way through to the physical implementation of a custom ASIC. Students will be introduced to our silicon-proven NanoSoC reference design, a generic microcontroller for research demonstrators that supports adding memory-mapped research experiments and components. Students will also learn about application specific SoC design through exploring the design and architecture of our MegaSoC reference design.

Danilo Pau is the Technical Director of System Research and Applications at STMicroelectronics, located in Agrate Brianza, Italy. He is an IEEE AAIA & ST Fellow and APSIPA Life Member.
Since joining SGS-THOMSON (which later became STMicroelectronics) in 1991, Danilo has been at the forefront of innovative projects. His work has spanned hardware design for computer vision tasks, including MPEG2 video memory reduction, video coding, and transcoding. Presently, he is deeply involved in advancing the ST unified AI core technology, which is integrated into ST development tools like STM32Cube.AI, STM32Cube.AI Developer Cloud, MEMs Studio and Stellar-Studio.AI.
Danilo is an active member of numerous technical committees, serving as a Technical Program Committee (TPC) member for the TinyML Symposium and Summit, as well as a member of the IEEE Computer Society Fellow Evaluating Committee. Danilo holds 78 European and 68 US patent applications. He authored over 190 scientific publications and 113 ISO/IEC/MPEG authored documents. He delivered more than 90 invited talks/seminars at various Universities and Conferences. Danilo’s favorite activity remains supervising undergraduate students and PhDs.

The technology of Tiny Machine Learning (TinyML) on embedded systems are evolving rapidly. Engineers and developers in these fields are constantly seeking innovative tools to enhance their productivity, speed, and creativity. The quest for groundbreaking applications in diverse sectors such as automotive, Internet of Things (IoT), medical, industrial, and robotics demands a seamless, end-to-end workflow of interoperable AI tools. The fragmentation of these tools, especially when it comes to compatibility with various hardware platforms, has been a significant barrier, stifling creativity, and the ability to meet customer needs effectively.

At ST, we devoted our best resources across product divisions and system research to create the Unified AI Core Technology. We are convinced that it solves above challenges and to act as the enabling unifying AI technology to serve all ST products such as micro-controllers and sensors. Furthermore, this technology interfaces the most widely used Deep Learning representation standards such as Google Keras, QKeras and Tensorflow Lite and the Open Neural Network Exchange (ONNX). It outputs optimized C code across heterogeneous instruction sets. Our technology comes with public APIs for a range of ST products, such as STM32, STM32N6, Stellar MCUs, and AI MEMs sensors, ensuring wide applicability. Developers can efficiently use the design environment of their choice.

Join me and delve into the intricacies of the Unified AI Core Technology and explore the workflow of interoperable AI tools for TinyML on sensors and MCUs.

Jose Miranda received his Ph.D. degree at the Microelectronic Design and Applications (DMA) research group, which belongs to Universidad Carlos III of Madrid. He is currently a Post-doc research assistant at the Embedded Systems Laboratory, EPFL. His research field comprises wireless sensors, embedded systems, wearable design, development and integration for safety applications, affective computing implementation into edge computing devices, and hardware acceleration. Regarding the development of wearable technology for safety applications, his main contribution relates to the design of new autonomous, smart, inconspicuous, connected, edge-computing-based, and wearable solutions, such as Bindi and VersaSens. His scholarly works in high-impact journals like IEEE Sensors Journal and IEEE Internet of Things Journal significantly contribute to physiological monitoring and IoT systems. Moreover, he is deeply involved in conducting advanced research in embedded systems, particularly focusing on RISC-V-based architectures using X-HEEP. This work includes exploring and developing new methodologies and technologies to enhance the capabilities of embedded systems across various applications. A significant part of his contributions lies in the development of open-source hardware and software, where he actively engages in the design and implementation of platforms that promote accessibility and modifiability for the broader research community.

Edge AI computing is targeting multiple domains nowadays, and a new set of complementary approaches have emerged as main avenues for designing novel accelerator- centric architectures for Cyber-Physical Systems (CPS). The first approach is based on integrating accelerators in computing systems as part of the micro-architecture comprising validated open hardware components (processors, memories, and peripherals) to derive heterogeneous systems-on-chip (SoC). The second is to model the accelerator characteristics inside the edge architecture as a separate module that serves as a co- processing system. In this lecture, Prof. Atienza will cover the pros and cons of these two approaches, focusing on recent works on the X-HEEP open-hardware architectural template and the design of different SoC flavors for in-memory Acceleration with tight processor Integration. These concepts will be presented in examples of different SoC architectures designed with industrial partners in the CPS context, emphasizing wearables in healthcare as a challenging application domain.

Elif Bilge Kavun holds the assistant professorship in Secure Intelligent Systems at the Faculty of Computer Science and Mathematics, University of Passau since October 2020. Previously, she was a Lecturer in Cybersecurity at The University of Sheffield (UK) and Digital Design Engineer for Crypto Cores at the Digital Security Solutions division, Infineon (Munich). She completed a PhD in Embedded Security in 2015 at the Faculty of Electrical Engineering and Information Technology, Ruhr University Bochum. Her research interests cover security of novel intelligent systems as well as traditional computing and embedded systems. She is also interested in secure hardware systems, design and implementation of cryptographic primitives, lightweight cryptography, and physical attacks & countermeasures.

As cyber-physical systems (CPS) become increasingly embedded in critical infrastructure, there is a growing need for encryption methods that are both secure and efficient. In these systems, the processing time required by cryptographic operations, particularly when implemented in hardware, is a key performance metric. Achieving low-latency encryption in CPS involves navigating complex trade-offs between factors such as circuit area, power consumption, and energy efficiency. This talk will focus on the challenges and trade-offs associated with implementing low-latency encryption in CPS, with an emphasis on block cipher design and hardware integration. It will review recent advancements and methodologies in low-latency cryptography, analyzing their strengths and weaknesses. Additionally, the impact of countermeasures against physical attacks on latency will be briefly discussed, providing a broad perspective on securing CPS environments.

Paolo Azzoni is the Secretary General of INSIDE Industry Association (formerly Artemis-IA),
the industry association that serves as the European Technology Platform for research, design and innovation on Intelligent Digital Systems and their technology ecosystems. INSIDE is one of the three private members of the Chips-JU, the tripartite partnership between the European Commission, the Participant States and private entities, mobilizing more than 11 billion euro to safeguard, consolidate, and strengthen the Electronic
Components and Systems value chain in Europe. In this context, he is the lead delegate in the Chips Ju Governing Board and the co-chairman of the ECS Strategic Research and Innovation Agenda, a funding-agnostic document describing the major challenges and priorities in the Electronic Components and Systems domain for the next 10 years. He is also the Head of European Technology Programmes at EUROTECH Group, planning and directing industrial research projects, in the areas of cyber-physical systems, intelligent systems, machine-to-machine technologies, edge computing, internet of things and digitalization solutions. Before joining EUROTECH, he was involved in academic lecturing and research in the areas of hardware formal verification, hardware/software co-design and co-simulation, advanced hardware architectures and operating systems. He holds a Master Degree in Computer Science and a second Master Degree in Intelligent Systems.

The speech provides an exploration of the electronic component and systems (ECS) engineering process, offering a comprehensive overview of its phases, from concept, to specification, to deployment, operation, maintenance, evolution and end of life. It explores the basics of each phase, illustrating their role, the relation with the ECS value chain, the existing standards and the adopted methods and tools. The speech addresses also the challenges the ECS domain is facing in terms of lack of skills and human resources, illustrating the opportunities introduced by generative AI and engineering automation. By the end, participants will gain an overview of the entire ECS engineering process, facilitating the positioning of the summer school demos and tutorials in the engineering process itself.

Thomas Pöppelmann is a Senior Principal Engineer at Infineon Technologies AG. He is leading the Security Innovation team and working as Platform Security Architect. His main area of work is the definition of security architectures and the development of concepts for secured cryptographic modules, security standardization, and innovation projects. His research interests are security architecture, physical protection of cryptographic implementations, post-quantum cryptography, and practical lattice-based cryptography. In 2015 he obtained his PhD (Dr.-Ing.) on practical lattice-based cryptography under the supervision of Prof. Dr.-Ing. Tim Güneysu at Ruhr-University Bochum.

This talk explores the challenges encountered when securing Cyber-Physical Systems (CPS) that are often build using microcontrollers and connectivity chips with WiFi or Bluetooth support. First, we will examine common security use-cases and problems that are faced in CPS. Then, we discuss current and emerging threats, including logical and physical attacks. We then explore security features and building blocks offered by MCUs that can be used to design a secured system. In addition, we will look into SW security frameworks like the Product Security Architecture (PSA) that offer easy to use access to isolation, secured storage and cryptographic functions.