In this tutorial we will start from Shor’s algorithm for prime decomposition to show how quantum computing has triggered the post-quantum revolution. We will discuss how a quantum computer works and how cryogenic electronics could make it reliable, thus moving it forward beyond
the current status of a pre-1947 machine. This proposal has introduced new constraints on noise and power dissipation to achieve highly sensitive circuits and systems, along with very precise timing capability. We advocate the use of CMOS technologies to achieve these goals, whereas the circuits will be operated at 2-10K. We believe that these, collectively known as cryo-CMOS circuits, will make future qubit arrays substantially more scalable than today, thus enabling a faster growth in qubit count. In the second part of the tutorial, we will discuss quantum key distribution systems from the perspective of hardware; we will look at the requirements in terms of optics and focus on single-photon detection. Due to the importance of this granularity and the need of compactness and reliability, SPADs and SNSPDs are the sensors of choice in this domain. We will discuss the challenges of designing complex single-photon detectors with picosecond timing resolutions in CMOS and in dedicated technologies based on deep-cryogenic operation, outlining several results achieved recently and future trends.

Edoardo Charbon received the Ph.D. in EECS from U.C. Berkeley in 1995. After 7 years in Silicon Valley as entrepreneur, he joined the faculty of EPFL, where he is full professor. From 2008 to 2016 he was with Delft University of Technology. Since 2014, he has pioneered the use of cryo-CMOS technology for quantum sensing/computing. He has co-authored over 500 papers and two books; he holds 31 patents. Dr. Charbon is the recipient of the 2023 IISS Pioneering Achievement Award, a distinguished lecturer of the IEEE Photonics Society, and a fellow of the IEEE and Optica.

This tutorial introduces LAKSA, the MLIR-based compiler developed in the MYRTUS project. It begins with MLIR basics and follows how LAKSA uses custom dataflow and HLS-oriented dialects to transform a CNN application toward FPGA implementation. Practical exercises introduce MLIR’s Python bindings and basic IR semantics, then explore dataflow semantics and show how compiler decisions affect accelerator design and resource use.
The tutorial also demonstrates Mocasin, a framework for modeling and simulating dataflow applications on heterogeneous platforms and exploring their mappings. Participants export an application model from LAKSA together with execution profiles, simulate mappings, and examine trade-offs such as execution time and energy. Together, the compiler and Mocasin workflows connect transformations in MYRTUS to platform-level mapping decisions.

Jiahong Bi received his Bachelor degree in Computer Science and Technology from Xidian University, China in June 2019, and his Master degree in Informatics from TU Dresden in December 2023. His Master Thesis is finished at the Chair for Compiler Construction, focusing on implementing and evaluating a custom FPGA back-end for a data flow model MLIR dialect, which utilizes High-Level Synthesis by CIRCT project and several AMD Xilinx tools. Jiahong finished his research project at CCC in January 2023, then continued working as a research student till April 2023. During this period, he helped implementing base2 and softfloat dialects, which were later used in the EVEREST project. Jiahong did a research work with Chair of Adaptive Dynamic System from 2022 to 2023 as well, from which he gained knowledge of FPGA hardware and HLS technology. After Master’s study Jiahong joined the chair as research assistant in February 2024, where he will work on project “MYRTUS: Multi-layer 360° dYnamic orchestrion and interopeRable design environmenT for compute-continUum Systems”, including defining novel programming methods and compiler infrastructures to deploy optimized software onto heterogeneous computing systems in mainly the embedded computing domains. His research interests include, but are not limited to, the representation and optimization of dataflow graphs across multiple abstraction levels. He is also interested in compilation for novel hardware architectures, such as the AI Engine in AMD XDNA and Wafer-Scale Chips such as WSE from Cerebras.

Robert Khasanov is a postdoctoral researcher at TU Dresden, Germany. He received his Bachelor’s and Master’s degrees in Computer Science from the Moscow Institute of Physics and Technology in 2012 and 2014, respectively, and his PhD degree in Computer Science from TU Dresden in 2025. Before starting his PhD studies, he held positions at Intel, where he worked on an optimizing binary translation system and later on the LLVM compiler project. His research interests include programming models, application mapping and scheduling, energy-efficient resource management for heterogeneous computing systems, and compiler technologies.

Large amounts of data are being collected thorough the new generation of digital medical devices, from diagnostic equipment to implantable devices. Increasingly, this data is being used to make decisions (such as diagnoses) on patients, and hence its security and privacy must be guaranteed. Often, Cyber-Physical Systems are used: for instance, an implantable automatic defibrillator, which makes an automatic decision to deliver an energy electric shock to the heart of someone who is in cardiac arrest. However, current security techniques have a high overhead, which makes them difficult to implement on constrained devices: the efficiency of the security techniques must therefore be increased, to enable the technology to be deployed more widely.

The EU-funded SECURED project aims to increase efficiency by scaling up multi-party computation, homomorphic encryption, data anonymisation, and private and unbiased AI, which are key security and privacy technique used on medical devices. In this tutorial, we will demonstrate how secure computation techniques including homomorphic encryption can be adopted in constrained settings, and applied to CPSs and medical devices. Students will be introduced to the basic of secure computation and will practice with state of the art libraries implementing the presented techniques.

Prof. Dr.-Ing. Elif Bilge Kavun is leader of the Secure Digital Systems (SDS) research group and Professor of Secure Digital Systems, Faculty of Computer Science, TU Dresden. Her research focuses on the security of digital systems, particularly secure hardware, resource-efficient cryptographic primitives, fault-tolerant architectures, and the protection of AI-driven systems from both internal and external manipulation. She aims to develop robust, trustworthy technologies that maintain their integrity even under adversarial or mission-critical conditions.

Dr. Apostolos Fournaris is a Principal Researcher (Research Associate Professor) in Industrial Systems Institute of Research Center ATHENA. He has worked for the Information and Communication Technologies Lab in Sophia Antipolis Hitachi Europe SAS European R-D Centre for two years on Hardware Security and Trust research. He has acted as a visiting lecturer at Monash University, Australia for 2 year and as an adjunct Assistant Professor in the University of Patras and University of Peloponesse for more than 10 years. His main research interests are IoT, Edge Embedded System/Cyber-Physical system hardware and software security with focus on industrial and critical infrastructures, Implementation attacks and resistance techniques on hardware or Software implemented security systems (Microarchitectural attacks (Rowhammer, cache attacks), Side channel attacks, fault injection attacks, Hardware Trojans) and Cryptographic Engineering on Public Key, PostQuantum cryptography and Homomorphic Encryption. He has published more than 100 research articles in international conferences and journals on hardware security and trust, cryptographic engineering and industrial CPS research topics.

Paolo Palmieri is a Tenured Assistant Professor (Lecturer above the Bar) in Cyber Security at University College Cork, Ireland, and holds a PhD in Cryptography from the Université catholique de Louvain in Belgium. His research work focuses on cryptography, privacy and anonymity and his interests include secure computation, privacy-enhancing technologies, anonymity protocols and de-anonymization, location privacy and the security of smart cities and e-health. He is a Funded Investigator in two large national research centers (CONNECT and Insight), and his research has been supported by several grants from Science Foundation Ireland, Enterprise Ireland and the EU Horizon Europe program.

Dr. Francesco Regazzoni is a Tenured UD1 at the University of Amsterdam (Amsterdam, The Netherlands) and also affiliated with Università della Svizzera Italiana (Lugano, Switzerland). He received his Master of Science degree from Politecnico di Milano and his PhD degree at Università della Svizzera Italiana. He has been assistant researcher at the Université Catholique de Louvain and at Technical University of Delft, and visiting researcher at several institutions, including NEC Labs America, Ruhr University of Bochum, EPF Lausanne, and NTU Singapore. His research interests are mainly focused on embedded systems security, covering in particular side channel attacks, electronic design automation for security, hardware Trojans, and low energy cryptography. He has published more than 130 peer reviewed papers in the area of security and design automation, (including CHES, DAC, DATE, HOST, EUROCRYPT and ASIACRYPT) and has been in the technical program committed of top conferences of the area (including CHES, DAC, DATE, ICCAD, HOST, and COSADE). He is currently the coordinator of the SECURED Horizon project.

This tutorial covers how to test the adversarial robustness of document understanding systems. We start with the basics of adversarial example optimization using gradient-based methods to change a model’s output with imperceptible perturbations. We then introduce the transformer architectures behind modern OCR-free document visual question answering (DocVQA) models, using Pix2Struct and Donut as examples, and explain how they jointly process image and text to generate answers. Finally, we connect these ideas to show how adversarial attacks can be crafted against document analysis systems, forcing targeted or corrupted answers through visually subtle perturbations, and discuss why this represents a new and largely unexplored attack surface with real-world consequences for automated document processing.

Maura Pintor is an Assistant Professor at the PRA Lab in the Department of Electrical and Electronic Engineering at the University of Cagliari, Italy. She received her PhD in Electronic and Computer Engineering from the University of Cagliari in 2022.
Her research focuses on adversarial machine learning, with a particular emphasis on evaluating, debugging, and improving the robustness of machine learning systems. Her work aims to make AI models more reliable, secure, and trustworthy in real-world settings.
She serves as an Area Chair for NeurIPS and as an Associate Editor for Pattern Recognition, and she is a Consulting Associate Editor for the IEEE Transactions on Information Forensics and Security (TIFS). She is a member of ACM, IEEE, the IEEE Information Forensics and Security Technical Committee, IAPR, and ELLIS, and she is currently vice-chair of IAPR TC1. She is also the main maintainer of the open-source library SecML-Torch, a framework for evaluating the adversarial robustness of deep learning models.