EVEREST Project tutorial: How to use HLS for building customized memory architectures


Many HPC applications are massively parallel and can benefit from the spatial parallelism offered by reconfigurable logic. While modern memory technologies can offer high bandwidth, designers must craft advanced communication and memory architectures for efficient data movement and on-chip storage. Addressing these challenges requires to combine optimizations that range from software to hardware design.

In this tutorial, we will give an overview of the challenges for generating massively parallel accelerators on FPGA for high-performance computing. We will also show how it is possible to combine compilers, source-to-source transformations, and commercial HLS tools for supporting the designer in the generation of high-performance memory architectures.


Stephanie Soldavini

Stephanie Soldavini is a PhD student in the Department of Electronics, Informatics and Bioengineering at Politecnico di Milano in Milan, Italy. She received her BS/MS in Computer Engineering from Rochester Institute of Technology (RIT) in 2019. Her masters thesis was on reduced-graph based optimizations for scheduling in high-level synthesis. Her research focuses on automatic hardware generation with a focus on memory aspects.

Christian Pilato

Christian Pilato is a Tenure-Track Assistant Professor at Politecnico di Milano. He was a Post-doc Research Scientist at Columbia University (2013-2016) and at the ALaRI Institute of the Università della Svizzera italiana (2016-2018). He was also a Visiting Researcher at New York University, Delft University of Technology, and Chalmers University of Technology. He has a Ph.D. in Information Technology from Politecnico di Milano (2011). His research interests focus on the design, optimization, and prototyping of heterogeneous system-on-chip architectures and reconfigurable systems, with emphasis on memory and security aspects. Starting from October 2020, he is the Scientific Coordinator of the H2020 EVEREST project. He served as program chair of EUC 2014 and he will be program chair of ICCD 2022. He is currently serving in the program and organizing committees of many conferences on EDA, CAD, embedded systems, and reconfigurable architectures (DAC, ICCAD, DATE, CASES, FPL, ICCD, etc.) He is a Senior Member of IEEE and ACM, and a Member of HiPEAC.

A Hands-on Lab on Evolvable Self-* CPSs


This lab aims to provide students with the practical skills necessary to design advanced Self-* Cyber-Physical Systems (CPSs), with a specific focus on applications in CPS control and image processing. Participants will have the opportunity to engage in hands-on exercises using Programmable Systems-on-Chip and simulators. This practical approach will offer valuable experience to participants, boosting their confidence in tackling real-world challenges in CPS design. By the end of the lab, students will have gained strong practical skills in designing advanced adaptive CPSs and the ability to apply their knowledge in real-world situations. This lab presents an invaluable opportunity for those seeking to expand and complementing the more theoretical view provided in the previous talk on Evolvable Self-* Systems.



Andrés Otero is a Telecommunications Engineer from the University of Vigo, where he graduated with Honors in 2007. He completed a Master’s and Doctorate in Industrial Electronics from the Universidad Politécnica de Madrid (UPM) in 2009 and 2014, respectively. He also has a specialist degree in Signal Processing. Currently, he serves as an Associate Professor at UPM. His areas of interest are embedded and/or reconfigurable systems, evolutionary computation, and machine learning at the Edge. It can be highlighted his experience, both in the design and implementation of FPGA-based systems, and his background in evolvable (and neuroevolvable) hardware. As a result of this work, he is the co-author of 19 articles in JCR-indexed journals, such as Transactions on Computers, Internet of Things Journal, and IEEE Sensors. In addition, he has published two book chapters and more than 40 communications at conferences such as FPL, ReConFig, AHS, or ARC. He is the co-author of the best papers in the ReConFig 2012 and ARC 2020 conferences. Andrés Otero regularly participates in the program committee of some of these conferences, being ReCoSoC 2017 program Chair and FPL track program chair in 2021. His research work has been carried out within the framework of public-funded projects, both at Spanish (DR.SIMON, DREAMS, REBECCA, PLATINO, and TALENT) and European (SMART, ENABLE-S3, ENVIGUARD, FASTCUDA, CERBERO, KYKLOS4.0, InSecTT, and A-IQReady) levels


Alfonso Rodríguez has a MSc on Industrial Electronics (2014) and a PhD on Electrical and Electronics Engineering (2020), both by Universidad Politécnica de Madrid (UPM). Currently, he works as an Assistant Professor at UPM and carries out its research activity as a member of the Center of Industrial Electronics (CEI-UPM).His main research interests are high-performance embedded systems, reconfigurable computing, open computer architectures (e.g., RISC-V), and edge AI/ML. His work is backed by 9 publications in JCR-indexed journals, as well as by 17 conference publications, 1 book, and 1 book chapter. He has actively participated in projects of different nature, both European (ENABLE-S3, CERBERO, KYKLOS 4.0, A-IQ Ready) and Spanish (REBECCA, PLATINO, TALENT, COGNITION). He is part of the steering committee of the DASIP workshop, which he also co-chaired in 2023.