Alberto L. Sangiovanni-Vincentelli is the Edgar L. and Harold H. Buttner Chair at the EECS Department, UC Berkeley. He graduated from the Politecnico di Milano in 1971. He co-founded Cadence and Synopsys, the two leading EDA companies. He is on the Board of Directors of Cadence, KPIT, Expert.ai, Cy4Gate, Exein, and Chairman of the Board of Quantum Motion, Phononic Vibes, Innatera and Phoelex. He is a member of the advisory board of Walden International and Xseed, of the Scientific Advisory Board of the Italian Institute of Technology and the Chair of the Strategic Board and of the International Advisory Board for the Milano Innovation District. He is a member of the Advisory Board of the Politecnico di Milano and honorary Professor at Politecnico di Torino. He was the President of the “Comitato Nazionale dei Garanti della Ricerca” and of the Strategy Committee of Fondo Strategico Italiano. He consulted for companies such as Intel, HP, Bell Labs, IBM, Lendlease, Samsung, UTC, Lutron, Kawasaki Steel, Fujitsu, Telecom Italia, Pirelli, GM, BMW, Mercedes, Magneti Marelli, and ST Microelectronics. He authored 19 books, 2 patents and over 1,000 papers. He is Fellow of the IEEE and ACM, and a member of the National Academy of Engineering. He is the recipient of several academic honors, and research awards including the IEEE/RSE Wolfson James Clerk Maxwell Medal “for groundbreaking contributions that have had an exceptional impact on the development of electronics and electrical engineering or related fields” and the BBVA Frontiers of Knowledge Award in the Information and Communication Technologies category with the following motivation: “for transforming chip design from a handcrafted process to the automated industry that power today’s electronic devices”. Alberto holds four Honorary Doctorates from University of Aalborg, KTH, AGH and University of Rome, Tor Vergata.

In the late 1980s and early 1990s, the most prestigious conferences and journals in electronic design were full of contributions related to the use of AI and in particular, of expert systems for layout, logic and high-level synthesis. The consensus was that the field of EDA was going to be nominated by EDAs. Several companies were founded in this domain. However, these approaches fell off from the interest of the community because of the superiority in quality of results demonstrated by tools that were based on specialized algorithms for layout and synthesis. Are we in the same situation today with Deep Learning and in general, Machine Learning? We will investigate how ML algorithms work and what are the problems to face when applying these techniques to CPS and electronic design.

Alfonso Rodríguez has a MSc on Industrial Electronics (2014) and a PhD on Electrical and Electronics Engineering (2020), both by Universidad Politécnica de Madrid (UPM). Currently, he works as an Assistant Professor at UPM and carries out its research activity as a member of the Center of Industrial Electronics (CEI-UPM).His main research interests are high-performance embedded systems, reconfigurable computing, open computer architectures (e.g., RISC-V), and edge AI/ML. His work is backed by 9 publications in JCR-indexed journals, as well as by 17 conference publications, 1 book, and 1 book chapter. He has actively participated in projects of different nature, both European (ENABLE-S3, CERBERO, KYKLOS 4.0, A-IQ Ready) and Spanish (REBECCA, PLATINO, TALENT, COGNITION). He is part of the steering committee of the DASIP workshop, which he also co-chaired in 2023.

One of the primary challenges in designing Cyber-Physical Systems (CPS) is providing them with the capability to adapt and respond to changes in the environment, system requirements, or operational conditions autonomously, without direct human intervention. The crucial aspect lies in the ability to reconfigure and self-adjust the systems to ensure optimal performance. In this talk, the focus will be on addressing adaptability in Self-* CPSs from an architectural perspective, combining evolutionary computation with artificial neural networks, commonly known as neuroevolution. Special emphasis will be given to various architectural approaches, including block-based, spiking, and deep neural networks, which serve as targets for continuous optimization and self-adaptation enabled by evolutionary algorithms. By embedding learning capabilities within CPSs, they can achieve self-optimization and self-adaptation, leading to continuous or lifelong learning. The talk will explore different applications in image processing, physical control, and reinforcement learning domains. This presentation will be closely connected to the viewpoints offered by the A-IQ Ready European project regarding neuromorphic and neuroevolutionary technologies. Participants will have the opportunity to gain knowledge about cutting-edge research and practical applications in the field of intelligent CPS.

Andrés Otero is a Telecommunications Engineer from the University of Vigo, where he graduated with Honors in 2007. He completed a Master’s and Doctorate in Industrial Electronics from the Universidad Politécnica de Madrid (UPM) in 2009 and 2014, respectively. He also has a specialist degree in Signal Processing. Currently, he serves as an Associate Professor at UPM. His areas of interest are embedded and/or reconfigurable systems, evolutionary computation, and machine learning at the Edge. It can be highlighted his experience, both in the design and implementation of FPGA-based systems, and his background in evolvable (and neuroevolvable) hardware. As a result of this work, he is the co-author of 19 articles in JCR-indexed journals, such as Transactions on Computers, Internet of Things Journal, and IEEE Sensors. In addition, he has published two book chapters and more than 40 communications at conferences such as FPL, ReConFig, AHS, or ARC. He is the co-author of the best papers in the ReConFig 2012 and ARC 2020 conferences. Andrés Otero regularly participates in the program committee of some of these conferences, being ReCoSoC 2017 program Chair and FPL track program chair in 2021. His research work has been carried out within the framework of public-funded projects, both at Spanish (DR.SIMON, DREAMS, REBECCA, PLATINO, and TALENT) and European (SMART, ENABLE-S3, ENVIGUARD, FASTCUDA, CERBERO, KYKLOS4.0, InSecTT, and A-IQReady) levels.

One of the primary challenges in designing Cyber-Physical Systems (CPS) is providing them with the capability to adapt and respond to changes in the environment, system requirements, or operational conditions autonomously, without direct human intervention. The crucial aspect lies in the ability to reconfigure and self-adjust the systems to ensure optimal performance. In this talk, the focus will be on addressing adaptability in Self-* CPSs from an architectural perspective, combining evolutionary computation with artificial neural networks, commonly known as neuroevolution. Special emphasis will be given to various architectural approaches, including block-based, spiking, and deep neural networks, which serve as targets for continuous optimization and self-adaptation enabled by evolutionary algorithms. By embedding learning capabilities within CPSs, they can achieve self-optimization and self-adaptation, leading to continuous or lifelong learning. The talk will explore different applications in image processing, physical control, and reinforcement learning domains. This presentation will be closely connected to the viewpoints offered by the A-IQ Ready European project regarding neuromorphic and neuroevolutionary technologies. Participants will have the opportunity to gain knowledge about cutting-edge research and practical applications in the field of intelligent CPS.

Elif Bilge Kavun holds the assistant professorship in Secure Intelligent Systems at the Faculty of Computer Science and Mathematics, University of Passau since October 2020. Previously, she was a Lecturer in Cybersecurity at The University of Sheffield (UK) and Digital Design Engineer for Crypto Cores at the Digital Security Solutions division, Infineon (Munich). She completed a PhD in Embedded Security in 2015 at the Faculty of Electrical Engineering and Information Technology, Ruhr University Bochum. Her research interests cover security of novel intelligent systems as well as traditional computing and embedded systems. She is also interested in secure hardware systems, design and implementation of cryptographic primitives, lightweight cryptography, and physical attacks & countermeasures.

Cyber physical systems (CPS) are becoming increasingly pervasive in modern society, encompassing a wide range of applications such as autonomous vehicles, industrial control systems, and smart healthcare devices. However, the interconnected nature of CPS makes them vulnerable to cyber attacks that can compromise their functionality and potentially cause physical harm to humans and infrastructure. Lightweight cryptography offers a solution to this problem by providing resource-efficient approaches for hardware and software components of CPS. This talk provides an overview of lightweight cryptography and its relevance to CPS security. We discuss the real-world challenges faced in securing CPS and explore the design and implementation aspects of lightweight cryptography primitives. The talk covers various aspects of lightweight cryptography, including key exchange, encryption, and authentication. We also highlight the importance of choosing the right cryptographic primitives based on the specific requirements of the CPS application. By the end of this talk, participants are expected have a solid understanding of the key concepts, challenges, and practical considerations related to lightweight cryptography for CPS security.

Giorgio Di Natale received the PhD in Computer Engineering from the Politecnico di Torino in 2003. He works as Director of Research for the French National Research Center (CNRS), and he is the director of the TIMA laboratory in Grenoble since January 2021. His research interests include hardware security and trust, secure circuits design and test, reliability evaluation and fault tolerance, software implemented hardware fault tolerance, and VLSI testing. He served as chair of the IEEE Computer Society TTTC, he is Golden Core member of the Computer Society and Senior member of the IEEE.

The increasing globalized supply chain of Integrated Circuits (ICs) has led to concerns regarding the security of fabricated circuits, particularly for cyber-physical systems that gather large amounts of sensitive data. Ensuring the trustworthiness and integrity of these circuits has become crucial due to the rising threat of IC piracy. This threat can impact the confidentiality of IC designs by stealing intellectual property, introduce malicious hardware and software to compromise their integrity, or disrupt the market by over-production, counterfeiting, or re-packaging. This talk will present a survey of existing vulnerabilities, as well as relevant research works and solutions.

Lana Josipović is an Assistant Professor in the Department of Information Technology and Electrical Engineering at ETH Zurich. Prior to joining ETH Zurich in January 2022, she received a Ph.D. degree in Computer Science from EPFL, Switzerland. Her research interests include reconfigurable computing and electronic design automation, with an emphasis on high-level synthesis techniques to generate hardware designs from high-level programming languages. She developed Dynamatic, an open-source high-level synthesis tool that produces dynamically scheduled circuits from C/C++ code. She is a recipient of the EDAA Outstanding Dissertation Award, Google Ph.D. Fellowship in Systems and Networking, Google Women Techmakers Scholarship, and Best Paper Award at FPGA’20.

High-level synthesis (HLS) tools generate digital hardware designs from high-level programming languages (e.g., C/C++) and promise to liberate designers from low-level hardware description details. Yet, HLS tools are still acceptable only for certain classes of applications and criticized for the difficulty of extracting the desired level of performance: generating good circuits still requires tedious code restructuring and hardware design expertise. In this talk, I will discuss the challenges and limitations of current FPGA-oriented HLS approaches. I will present a new HLS methodology that aims to overcome these issues by producing dynamically scheduled, dataflow circuits out of C/C++ code; the resulting circuits achieve good performance out of the box and realize behaviors that are beyond the capabilities of standard HLS tools. I will outline mathematical models to optimize the performance and area of the resulting circuits, as well as techniques to achieve characteristics that standard HLS cannot support, such as out-of-order memory accesses and speculative execution. These contributions redefine the HLS paradigm by introducing characteristics of modern superscalar processors to hardware designs; such behaviors are key for specialized computing to be successful in new contexts and broader application domains.

Luca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Universita di Bologna. He received a PhD from Stanford University. Dr. Benini’s research interests are in energy-​efficient parallel computing systems, smart sensing micro-​systems and machine learning hardware. He is a Fellow of the IEEE, of the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award, the 2020 EDAA achievement Award, the 2020 ACM/IEEE A. Richard Newton Award and the 2023 IEEE CS E.J. McCluskey Award.

The next wave of “Extreme Edge AI” pushes signal processing and machine learning aggressively towards sensors and actuators, with sub mW (TinyML) power budgets, while at the same time raising the bar in terms of accuracy and flexibility. To succeed in this balancing act, we need principled ways to walk the line between general-purpose and highly specialized architectures.
In the talk, I will detail on how to walk the line, with examples form the 50+ chips tape-out experience of the open PULP (parallel ultra-low power) platform, based on RISC-V processors, coupled with domain-specific acceleration engines for TinyML and signal processing. The key techniques covered will be: (a) processor specialization via instruction extension, (b) efficient shared-memory parallel processing with low-power processor clusters, (c) heterogeneous computing: tightly coupled hardware accelerators and processors.

Michaela Blott works as a Senior Fellow with AMD, Dublin, Ireland, where she heads a team of international scientists driving exciting research to define new application domains for Xilinx devices, such as machine learning, in both embedded and hyperscale deployments. She earned a PhD from Trinity College Dublin and brings over 25 years of leading edge computer architecture and advanced FPGA and board design, research institutions (ETH Zurich and Bell Labs) and development organizations. She is heavily involved with the international research community, industry advisor on numerous EU projects, and winner of the WMB award in 2015 and finalist of VentureBeat Women in AI’2019, and Women in Technology‘2019 awards.

In the context of AI, we face a plethora of challenges that extend beyond the widely discussed performance scalability required to meet the growing demands of compute and storage in the latest models. These challenges encompass sustainability, pervasiveness, agility, and diversity, which is needed to cater to a constantly evolving range of applications and algorithms from edge to cloud. In this talk, we explore how adaptive devices and agile compiler stacks can provide solutions by delivering post-production hardware specialization and co-designed algorithms. This results in highly optimized AI systems which not only provide the necessary performance scalability but also bring a reduction in carbon footprint while addressing the needs of a broad range of diverse applications and with the necessary agility.