This tutorial shows the multi-grain reconfiguration capabilities of the combined MDC-ARTICo3 flow in an image-processing application scenario, and it is divided in three parts:

1) Composition of the dataflow-based ARTICo3 compliant CGR accelerators, adopting MDC Tool.
2) Composition of DPR-enabled computing systems, using the CGR-based accelerators and the ARTICo3 framework.
3) Running on Board. In order to switch from one kernel to another, the user can decide to use the DPR approach of ARTICo3 to completely change the logic instantiated in each slot, or to use the CGR approach of the MDC- generated accelerators to multiplex the internal datapath of the accelerators.
As a result, it is possible to see, in real time, the runtime overheads of each type of reconfiguration mechanism. Additional adaptivity evaluation can be performed by changing the working point of the application, which is based on several parameters: input image size, number of hardware accelerators used to exploit data-level parallelism.