Alberto L. Sangiovanni-Vincentelli is the Edgar L. and Harold H. Buttner Chair at the EECS Department, UC Berkeley. He graduated from the Politecnico di Milano in 1971. He co-founded Cadence and Synopsys, the two leading EDA companies. He is on the Board of Directors of Cadence, KPIT, Expert.ai, Cy4Gate, Exein, and Chairman of the Board of Quantum Motion, Phononic Vibes, Innatera and Phoelex. He is a member of the advisory board of Walden International and Xseed, of the Scientific Advisory Board of the Italian Institute of Technology and the Chair of the Strategic Board and of the International Advisory Board for the Milano Innovation District. He is a member of the Advisory Board of the Politecnico di Milano and honorary Professor at Politecnico di Torino. He was the President of the “Comitato Nazionale dei Garanti della Ricerca” and of the Strategy Committee of Fondo Strategico Italiano. He consulted for companies such as Intel, HP, Bell Labs, IBM, Lendlease, Samsung, UTC, Lutron, Kawasaki Steel, Fujitsu, Telecom Italia, Pirelli, GM, BMW, Mercedes, Magneti Marelli, and ST Microelectronics. He authored 19 books, 2 patents and over 1,000 papers. He is Fellow of the IEEE and ACM, and a member of the National Academy of Engineering. He is the recipient of several academic honors, and research awards including the IEEE/RSE Wolfson James Clerk Maxwell Medal “for groundbreaking contributions that have had an exceptional impact on the development of electronics and electrical engineering or related fields” and the BBVA Frontiers of Knowledge Award in the Information and Communication Technologies category with the following motivation: “for transforming chip design from a handcrafted process to the automated industry that power today’s electronic devices”. Alberto holds four Honorary Doctorates from University of Aalborg, KTH, AGH and University of Rome, Tor Vergata.

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Danilo Pau is the Technical Director of System Research and Applications at STMicroelectronics, located in Agrate Brianza, Italy. He is an IEEE AAIA & ST Fellow and APSIPA Life Member.
Since joining SGS-THOMSON (which later became STMicroelectronics) in 1991, Danilo has been at the forefront of innovative projects. His work has spanned hardware design for computer vision tasks, including MPEG2 video memory reduction, video coding, and transcoding. Presently, he is deeply involved in advancing the ST unified AI core technology, which is integrated into ST development tools like STM32Cube.AI, STM32Cube.AI Developer Cloud, MEMs Studio and Stellar-Studio.AI.
Danilo is an active member of numerous technical committees, serving as a Technical Program Committee (TPC) member for the TinyML Symposium and Summit, as well as a member of the IEEE Computer Society Fellow Evaluating Committee. Danilo holds 78 European and 68 US patent applications. He authored over 190 scientific publications and 113 ISO/IEC/MPEG authored documents. He delivered more than 90 invited talks/seminars at various Universities and Conferences. Danilo’s favorite activity remains supervising undergraduate students and PhDs.

The technology of Tiny Machine Learning (TinyML) on embedded systems are evolving rapidly. Engineers and developers in these fields are constantly seeking innovative tools to enhance their productivity, speed, and creativity. The quest for groundbreaking applications in diverse sectors such as automotive, Internet of Things (IoT), medical, industrial, and robotics demands a seamless, end-to-end workflow of interoperable AI tools. The fragmentation of these tools, especially when it comes to compatibility with various hardware platforms, has been a significant barrier, stifling creativity, and the ability to meet customer needs effectively.

At ST, we devoted our best resources across product divisions and system research to create the Unified AI Core Technology. We are convinced that it solves above challenges and to act as the enabling unifying AI technology to serve all ST products such as micro-controllers and sensors. Furthermore, this technology interfaces the most widely used Deep Learning representation standards such as Google Keras, QKeras and Tensorflow Lite and the Open Neural Network Exchange (ONNX). It outputs optimized C code across heterogeneous instruction sets. Our technology comes with public APIs for a range of ST products, such as STM32, STM32N6, Stellar MCUs, and AI MEMs sensors, ensuring wide applicability. Developers can efficiently use the design environment of their choice.

Join me and delve into the intricacies of the Unified AI Core Technology and explore the workflow of interoperable AI tools for TinyML on sensors and MCUs.

David Atienza is a professor of Electrical and Computer Engineering, Head of the Embedded Systems Laboratory (ESL) and Scientific Director of the EcoCloud Sustainable Computing Center at EPFL, Switzerland. His research interests include system-level design methodologies for multi-processor system-on-chip (MPSoC) targeting low-power Cyber-Physical Systems (CPS) and energy-efficient computing servers. His latest works include new2.5D/3D power/thermal-aware design and architectures for MPSoCs targeting edge AI systems, as well as HW/SW co-design and AI-based multi-level optimization for sustainable computing in the Internet of Things (IoT) context.

Prof. David Atienza has co-authored over 400 papers, one book, and 14 patents in these previous areas. He has also received multiple recognitions and awards, among them the ICCAD 10-Year Retrospective Most Influential Paper Award in 2020, the Design Automation Conference (DAC) Under-40 Innovators Award in 2018, and IEEE CEDA and ACM SIGDA EarlyCareer Awards on EDA tools and systems research. He is a Fellow of IEEE and of ACM, andChair of the European Design Automation Association (EDAA). He is currently the Editor-in-Chief of IEEE Trans. on CAD (T-CAD) and ACM Computing Surveys.

Edge AI computing is targeting multiple domains nowadays, and a new set of complementary approaches have emerged as main avenues for designing novel accelerator- centric architectures for Cyber-Physical Systems (CPS). The first approach is based on integrating accelerators in computing systems as part of the micro-architecture comprising validated open hardware components (processors, memories, and peripherals) to derive heterogeneous systems-on-chip (SoC). The second is to model the accelerator characteristics inside the edge architecture as a separate module that serves as a co- processing system. In this lecture, Prof. Atienza will cover the pros and cons of these two approaches, focusing on recent works on the X-HEEP open-hardware architectural template and the design of different SoC flavors for in-memory Acceleration with tight processor Integration. These concepts will be presented in examples of different SoC architectures designed with industrial partners in the CPS context, emphasizing wearables in healthcare as a challenging application domain.